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GPL Cver is an open-source, interpreted Verilog simulator by Pragmatic C SoftwareOpen-source interpreted Verilog simulator with a feature set and performance similar to Verilog-XL. Implements all IEEE 1364-1995 features along with some Verilog-2001 features. Full support for Verilog PLIs.
Version: 2.12a License: GPL-2
GitHub
10 build(s) found
| Builder | Build Number | Start Time | Elapsed Time | Watcher | Build Status |
|---|---|---|---|---|---|
| 15 | 8941 | 2024-10-09 23:38:44 | 0:00:27 | 835 | build successful |
| 14.arm64 | 9613 | 2024-01-21 1:44:37 | 0:00:14 | 4307 | build successful |
| 14 | 13778 | 2023-11-25 4:17:56 | 0:03:34 | 2177 | build successful |
| 13.arm64 | 9605 | 2023-03-07 7:04:40 | 0:00:16 | 4051 | build successful |
| 13 | 10345 | 2023-01-02 1:19:09 | 0:00:58 | 1364 | build successful |
| 12 | 13130 | 2022-01-12 18:13:53 | 0:00:32 | 3358 | build successful |
| 12.arm64 | 26974 | 2021-11-24 4:01:15 | 0:00:17 | 1519 | build successful |
| 11 | 21418 | 2021-02-10 17:18:28 | 0:01:05 | 2890 | build successful |
| 11.arm64 | 11733 | 2021-02-10 10:49:38 | 0:00:19 | 3030 | build successful |
| 10.15 | 19366 | 2020-01-05 21:34:05 | 0:01:56 | 1835 | build successful |