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Icarus Verilog

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format.

Version: 12.0 License: GPL-2+ GitHub
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139 build(s) found

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Builder Build Number Start Time Elapsed Time Watcher Build Status
10.7 86830 2022-01-24 11:54:21 0:04:46 27010 failed install-port
12 5147 2021-12-03 0:01:52 0:02:33 852 failed install-port
10.14 105948 2021-11-15 14:36:15 0:02:05 33257 failed install-port
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11.arm64 34369 2021-11-13 22:35:32 0:00:29 12253 failed install-port
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10.6 44267 2021-11-13 17:45:55 0:08:50 24075 failed install-port
10.6.x86_64 79528 2021-11-13 17:12:00 0:06:42 24047 failed install-port
10.10 161763 2021-11-13 17:06:53 0:01:49 51672 failed install-port
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10.7 49566 2021-04-10 21:08:45 0:07:28 16647 build successful
10.8 43305 2021-04-10 17:02:08 0:02:35 14507 build successful
10.8 43304 2021-04-10 16:27:55 0:01:38 14504 failed install-port
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11 21562 2021-02-13 9:03:18 0:03:15 2922 build successful
10.8 38377 2021-02-11 19:39:19 0:01:37 12781 failed install-port
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11.arm64 11786 2021-02-11 11:25:33 0:01:08 3062 build successful
10.12 121556 2020-07-09 13:19:40 0:01:46 33954 build successful
10.7 24897 2020-06-28 16:18:48 0:00:53 7391 failed install-port
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10.10 117513 2020-06-20 0:17:55 0:01:34 35015 build successful
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10.7 16983 2020-02-03 7:28:29 0:00:51 3944 failed install-port
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10.15 17047 2019-12-27 14:55:03 0:02:42 1728 build successful
10.5_ppc 91346 2019-01-24 1:06:47 0:07:41 20806 build successful