verilator (science/verilator) Updated: 7 months, 1 week ago Add to my watchlist

Verilog compiler and simulator

Verilator is a Verilog compiler and simulator.

Version: 5.028 License: (LGPL-3 or Artistic-2) GitHub
Displaying statistics for 1,152 users who made submissions during: until

Statistics for selected duration

2025-Mar-20 to 2025-Apr-19


Total Installations 2
Requested Installations 2


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MacPorts
Port Information was updated:
2 hours ago
81f7e40a

Most recent build (in app's database) ran:
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